Timing generation circuit, display device, and mobile terminal

ABSTRACT

A timing generating circuit with low power consumption and a small layout area, a display apparatus including the timing generating circuit as one peripheral driving circuit, and a portable terminal including the display apparatus as a display output section are provided. In the timing generating circuit, which is formed on an insulating substrate and generates output pulses SRFF 1 out to SRFFnout having different frequencies based on a master clock MCK, a clock generating circuit ( 11 ) generates an operating clock having a lower frequency than the master clock MCK frequency. Then, a counter section ( 12 ) operates based on this operating clock and successively outputs shifted pulses S/R 1 out to S/Rmount from shift registers ( 121 - 1 ) to ( 121 - m ). An output pulse generating section ( 13 ) generates output pulses SF 1 out to SFnout based on combinations of the shifted pulses S/R 1 out to S/Rmount.

TECHNICAL FIELD

[0001] The present invention relates to a timing generating circuit, adisplay apparatus, and a portable terminal and, particularly, to atiming generating circuit formed including.transistors having widevariations in their device properties on an insulating substrate, adisplay apparatus including this timing generating circuit as oneperipheral driving circuit, and a portable terminal including thisdisplay apparatus as a display screen component.

BACKGROUND ART

[0002] A timing generating circuit having a counter circuit structureshown in FIG. 6 is known. Specifically, this known timing generatingcircuit includes a counter circuit in which n stages of shift registers(S/R) 101-1 to 101-n are cascaded. As each CK input to the shiftregisters 101-1 to 101-n, a master clock MCK and its negative-phaseclock XMCK are provided. When a start pulse ST is input to the firststage shift register 101-1, the shift registers 101-1 to 101-n performshift operations in synchronism with the master clock MCK and XMCK tooutput shifted pulses as output pulses from each output terminalthereof.

[0003] If the above described timing generating circuit is formedincluding transistors having wide variations in their device propertiesand a high threshold Vth, for example, thin film transistors (TFTs) onan insulating substrate, such as a glass substrate, a matter of concernis that high (fast) frequencies in the master clock MCK and XMCK maycause problems in the counter operation (leave no operating margin). Ifthe counter operates with such a high frequency, the power consumptionin the timing generating circuit would increase. Further, a large layoutarea is needed since shift registers are required depending on theperiod of the output pulses and the TFTs have a larger process rulecompared with the case where silicon is used.

[0004]FIG. 7 shows the circuit structure of another known timinggenerating circuit. This timing generating circuit may have anasynchronous counter circuit structure including three T-type flip-flops(hereinafter referred to as TFF) 102-1, 102-2, and 102-3 in which alower-bit output from one TFF is a higher-bit input to another TFF. Thisknown timing generating circuit, however, may malfunction due to delayvariations in the TFFs 102-1, 102-2, and 102-3.

[0005] In view of the above mentioned problems, it is an object of thepresent invention to provide a timing generating circuit with low powerconsumption and small layout area even when transistors having widevariations in their device properties and a large process rule are used,a display apparatus including this timing generating circuit as oneperipheral driving circuit, and a portable terminal including thisdisplay apparatus as a display output component.

DISCLOSURE OF INVENTION

[0006] The present invention provides a timing generating circuit havingclock generating means formed on an insulating substrate for generatingan operating clock based on a master clock input from the outside, theoperating clock having a lower frequency than the master clockfrequency; and signal generating means for generating multiple timingsignals having different frequencies based on the operating clockgenerated by the clock generating means. This timing generating circuitis used in a display apparatus. In the display apparatus, the timinggenerating circuit is disposed on the same transparent insulatingsubstrate as a display section and generates multiple timing signalshaving different frequencies required for driving the display section.The display apparatus including this timing generating circuit isdisposed in a portable terminal, typified by a personal digitalassistant (PDA) and a mobile phone, as a display screen componentthereof.

[0007] In the above described timing generating circuit, the displayapparatus including this timing generating circuit as one peripheralcircuit, or the portable terminal including this display apparatusdisposed therein as the display screen component, firstly, the clockgenerating means converts the master clock into the operating clockhaving a lower frequency than the master clock frequency, and then thesignal generating means generates the multiple timing signals based onthe operating clock having the lower frequency. This enables a slowoperating speed, thus allowing stable operation and reduced powerconsumption. Further, since shift registers are not required dependingon the period of the timing signals, the structure has a small number ofstages. Therefore, a small layout area is achieved even when transistorshaving wide variations in their device properties and a large processrule are used for forming circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a block diagram showing a typical structure of a timinggenerating circuit of an embodiment of the present invention.

[0009]FIG. 2 is a timing chart for explanation of the circuit operationof the timing generating circuit of the embodiment.

[0010]FIG. 3 is a block diagram showing a typical structure of a liquidcrystal display apparatus of the present invention.

[0011]FIG. 4 is a circuit diagram showing a typical pixel structure.

[0012]FIG. 5 is an external view showing the schematic structure of aPDA of the present invention.

[0013]FIG. 6 is a circuit diagram showing a known timing generatingcircuit.

[0014]FIG. 7 is a circuit diagram of another known timing generatingcircuit.

BEST MODE FOR CARRYING OUT THE INVENTION

[0015] An embodiment of the present invention will be illustrated withreference to the drawings.

[0016]FIG. 1 is a block diagram of the timing generating circuit of theembodiment of the present invention. As is apparent from FIG. 1, thetiming generating circuit of this embodiment has a clock generatingsection 11, a counter section 12, and an output pulse generating section13. It is based on the premise that the timing generating circuit isformed including transistors, for example, TFTs, that have widevariations in their device properties and a large process rule on aninsulating substrate, such as a glass substrate.

[0017] The clock generating section 11 may include four dividingcircuits 111 to 114 and a start pulse generating circuit 115. The fourdividing circuits 111 to 114 are cascaded and divide a master clock MCKinput to the first stage thereof to generate an operating clock having alower frequency than the master clock MCK frequency. The start pulsegenerating circuit 115 generates a start pulse ST every 1H period (H isa horizontal period) based on, for example, a horizontal synchronizationsignal Hsync and the master clock MCK.

[0018] The counter section 12 includes m shift registers (S/R) 121-1 to121-m, which are cascaded. The operating clock generated in the clockgenerating section 11 is input to the shift registers 121-1 to 121-m aseach ck input. When the start pulse ST generated in the start pulsegenerating circuit 115 is input to the first stage shift register 121-1,the shift registers 121-1 to 121-m perform shift operations insynchronism with the operating clock to successively output shiftedpulses from each output terminal thereof.

[0019] The output pulse generating section 13 includes n set reset (SR)flip-flops (hereinafter referred to as SRFF) 131-1 to 131-n. The shiftedpulses output from the shift registers 121-1 to 121-m in the countersection 12 are supplied to the SRFFs 131-1 to 131-n in any combinationas each set input and reset input thereof.

[0020] Examples of such a combination are as follows: for the SRFF131-1, a shifted pulse from the shift register 121-1 as a set input anda shifted pulse from the shift register 121-m as a reset input; and forthe SRFF 131-2, a shifted pulse from the shift register 121-2 as a setinput and a shifted pulse from the shift register 121-3 as a resetinput. Examples for the SRFFs 131-3 to 131-n-1 are omitted here. For theSRFF 131-n, a shifted pulse from the shift register 121-1 as a set inputand a shifted pulse from the shift register 121-2 as a reset input maybe provided.

[0021] The counter section 12 and the output pulse generating section(signal generating section) 13 constitute signal generating means forgenerating multiple timing signals (output pulses) having differentfrequencies based on the operating clock generated by the clockgenerating section 11.

[0022] The circuit operation of the timing generating circuit of theembodiment having the above described arrangement will now be describedwith reference to the timing chart shown in FIG. 2.

[0023] In the clock generating section 11, the dividing circuits 111 to114 generate the operating clock having a lower (slower) frequency thanthe master clock MCK frequency, specifically, one eighth of the masterclock MCK frequency, by dividing the master clock MCK four times. Thestart pulse generating circuit 115 generates the start pulse whose pulsewidth is, for example, five times wider than that of the master clockMCK every 1H period in synchronism with the horizontal synchronizationsignal Hsync.

[0024] Upon input of the start pulse to the first stage shift register121-1, the counter section 12 performs count operations and successivelyoutputs shifted pulses S/R1out, S/R2out, . . . , S/Rmout, each of whosepulse width is the same as that of the operating clock, in synchronismwith the operating clock generated by the clock generating section 11.

[0025] In the output pulse generating section 13, the SRFF 131-1 is setwith the shifted pulse S/R1out from the shift register 121-1 and isreset with the shifted pulse S/Rmout from the shift register 121-m,thereby generating an output pulse SRFF1out, which is at a high levelfor the duration between the rise time of the shifted pulse S/R1out andthat of the shifted pulse S/Rmout. The SRFF 131-2 is set with theshifted pulse S/R2out from the shift register 121-2 and is reset withthe shifted pulse S/R3out from the shift register 121-3, therebygenerating an output pulse SRFF2out, which is at a high level for theduration between the rise time of the shifted pulse S/R2out and that ofthe shifted pulse S/R3out.

[0026] The explanation of the SRFFs 131-3 to 131-n-1 is omitted. TheSRFF 131-n is set with the shifted pulse S/R1out from the shift register121-1 and is reset with the shifted pulse S/R2out from the shiftregister 121-2, thereby generating an output pulse SRFFnout, which is ata high level for the duration between the rise time of the shifted pulseS/R1out and that of the shifted pulse S/R2out.

[0027] As discussed above, the timing generating circuit, which isformed on the insulating substrate and generates the multiple outputpulses SRFF1out to SRFFnout having different frequencies based on themaster clock MCK, firstly generates the operating clock having the lowerfrequency than the master clock MCK frequency, and then generates theoutput pulses SRFF1out to SRFFnout based on the generated operatingclock having the lower frequency. This enables a slow operating speed inthe counter section 12, thus allowing a wide operating margin in thecounter section 12, stable operation, and also reduced powerconsumption. Moreover, in this embodiment, since the start pulse ST isgenerated every 1H period, the output pulses having any generated timingcan be generated every 1H period.

[0028] Since shift registers are not required depending on the period ofthe output pulses, the counter section 12 has the small number ofstages. Therefore, a small layout area is achieved even when TFTs thathave wide variations in their device properties and a large process ruleare used for forming circuits on the insulating substrate. The operatingclock is generated by dividing the master clock MCK four times in thisembodiment so that both the power consumption and the layout area arereduced to about a quarter, respectively, as compared with the casewhere there is no dividing.

[0029] This embodiment is described with such a structure in which theoperating clock is generated by dividing the master clock MCK fourtimes, but it is not limited to division by four. Generating anoperating clock having a further lower frequency by increasing thenumber of divisions achieves larger reductions in the power consumptionand the layout area.

[0030] The start pulse ST is generated every 1H period in synchronismwith the horizontal synchronization signal Hsync in this embodiment, butthe start pulse ST may be generated every 1V period (V is a verticalperiod) in synchronism with a vertical synchronization signal Vsync. Inthis case, the output pulses having any generated timing can begenerated every 1V period.

[0031] The timing generating circuit according to the above embodimentis suitable for use as a timing generator that generates various timingsignals required for driving a display section based on a master clockMCK externally input to the substrate of, for example, adriving-circuit-integrated display apparatus, which peripheral drivingcircuits are integrally formed on the same transparent insulatingsubstrate as the display section having a matrix of pixels.

[0032] [Application]

[0033]FIG. 3 is a block diagram showing a typical structure of thedisplay apparatus, for example, a liquid crystal display apparatus, ofthe present invention. Referring to FIG. 3, a display section (pixelsection) 32 having a matrix of pixels is formed on a transparentinsulating substrate, for example, a glass substrate 31. The glasssubstrate 31 faces another glass substrate at a predetermined spacing.These substrates contain a liquid crystal material therebetween, therebyconstituting a display panel (LCD panel).

[0034]FIG. 4 is a circuit diagram showing a typical structure of eachpixel of the display section 32. A pixel 50 of the matrix of pixelsincludes a thin film transistor (TFT) 51, which is a pixel transistor, aliquid crystal cell 52, whose pixel electrode is connected to a drainelectrode of the TFT 51, and a storage capacitor 53, one electrodethereof being connected to the drain electrode of the TFT 51. The liquidcrystal cell 52 functions as a liquid crystal capacitance generatedbetween the pixel electrode and the opposite electrode.

[0035] In this pixel structure, a gate electrode of the TFT 51 isconnected to a gate line (scanning line) 54, while a source electrode ofthe TFT 51 is connected to a data line (signal line) 55. The oppositeelectrode of the liquid crystal cell 52 is connected to a VCOM line 56,which is common to each pixel. Through the VCOM line 56, a commonvoltage VCOM (VCOM electric potential) is supplied to the oppositeelectrode of the liquid crystal cell 52. This supply is common to eachpixel. The other electrode (the terminal of the opposite electrode) ofthe storage capacitor 53 is connected to a CS line 57, which is commonto each pixel.

[0036] When IH (H is a horizontal period) inversion driving or 1F (F isa field period) inversion driving is performed, a display signal writtenin each pixel is inverted relative to the VCOM electric potential. WhenVCOM inversion driving, which inverts the polarity of the VCOM electricpotential every 1H or 1F, is used in combination with the IH inversionor the 1F inversion, the polarity of a CS electric potential supplied tothe CS line 57 is inverted in synchronism with the VCOM electricpotential. The liquid crystal display apparatus according to the presentinvention is not limited to the VCOM inversion driving.

[0037] Referring back to FIG. 3, an interface (IF) circuit 33, a timinggenerator (TG) 34, and a reference voltage driver 35 may be disposed onthe glass substrate 31, which the display section 32 is disposedthereon, to the left of the display section 32. A horizontal driver 36may be disposed on the glass substrate 31 above the display section 32.A vertical driver 37 may be disposed on the glass substrate 31 to theright of the display section 32. A CS driver 38 and a VCOM driver 39 maybe disposed on the glass substrate 31 below the display section 32.These peripheral driving circuits are made with low-temperaturepoly-silicon or continuous grain (CG) silicon together with the pixeltransistors of the display section 32.

[0038] In the liquid crystal display apparatus as described above, amaster clock MCK, a horizontal synchronization pulse Hsync, a verticalsynchronization pulse Vsync, and display data Data of parallel input red(R), green (G), and blue (B), all of which have a low-voltage amplitude(e.g. 3.3 V amplitude), are input to the glass substrate 31 from theoutside of the substrate through a flexible cable (substrate) 40 andtheir levels are shifted (converted) to a high-voltage amplitude (e.g.6.5 V) in the interface circuit 33.

[0039] The level-shifted master clock MCK, horizontal synchronizationpulse Hsync, and vertical synchronization pulse Vsync are supplied tothe timing generator 34. The timing generator 34 generates varioustiming pulses required for driving the reference voltage driver 35, thehorizontal driver 36, the vertical driver 37, the CS driver 38, and theVCOM driver 39 based on the master clock MCK, the horizontalsynchronization pulse Hsync, and the vertical synchronization pulseVsync. The level-shifted display data Data is reduced to a low-voltageamplitude of 0 V to 3.3 V and is supplied to the horizontal driver 36.

[0040] The horizontal driver 36 may include a horizontal shift register361, a data-sampling latch circuit 362, and a digital-to-analog (DA)conversion circuit (DAC) 363. The horizontal shift register 361 performsa shift operation in response to a horizontal start pulse HST suppliedfrom the timing generator 34 and generates sampling pulses, each ofwhich is successively transferred in one horizontal period, insynchronism with a horizontal clock pulse HCK supplied from the timinggenerator 34.

[0041] The data-sampling latch circuit 362 successively samples thedisplay data Data supplied from the interface circuit 33 in synchronismwith the sampling pulses generated in the horizontal shift register 361every horizontal period and latches the sampled display data Data. Thislatched digital data for one line is further sent to a line memory (notshown) in a horizontal blanking period. Then, this digital data for oneline is converted to analog display signals in the DA conversion circuit363.

[0042] The DA conversion circuit 363 may have such a structure that itselects a reference voltage corresponding to the digital data fromreference voltages corresponding to the number of gradations suppliedfrom the reference voltage driver 35 and outputs the selected referencevoltage as the analog display signals. The analog display signals Sigfor one line, which are output from the DA conversion circuit 363, areoutput to n data lines 55-1 to 55-n, corresponding to the number n ofhorizontal pixels of the display section 32.

[0043] The vertical driver 37 includes a vertical shift register and agate buffer. In this vertical driver 37, the vertical shift registerperforms a shift operation in response to a vertical start pulse VSTsupplied from the timing generator 34 and generates scanning pulses,each of which is successively transferred in one vertical period, insynchronism with a vertical clock pulse VCK supplied from the timinggenerator 34. These generated scanning pulses are successively output tom gate lines 54-1 to 54-m, corresponding to the number m of verticalpixels of the display section 32, through the gate buffer.

[0044] When the scanning pulses are successively output to the gatelines 54-1 to 54-m by this vertical scanning of the vertical driver 37,the pixels of the display section 32 are selected line by line insequence. The analog display signals Sig for one line output from the DAconversion circuit 363 are sequentially written in the selected pixelsfor one line through the data lines 55-1 to 55-n. Such a writingoperation is repeated for every line, resulting in display for onescreen.

[0045] The CS driver 38 generates the CS electric potential describedabove and provides it to the other electrode of the storage capacitor 53through the CS line 57 shown in FIG. 4. This provision is common to eachpixel. Assuming that the display signals have an amplitude of 0 V to 3.3V, the CS electric potential repeats an alternating-current inversionbetween a low level of 0 V (ground level) and a high level of 3.3 V whenthe VCOM inversion driving is adopted.

[0046] The VCOM driver 39 generates the VCOM electric potentialdescribed above. The VCOM electric potential from the VCOM driver 39 isoutput to the outside of the glass substrate 31 through the flexiblecable 40 and is then transferred to a VCOM adjustment circuit 41. ThisVCOM electric potential is sent back to the glass substrate 31 throughthe flexible cable 40 and is then supplied to the opposite electrode ofthe liquid crystal cell 52 through the VCOM line 56 shown in FIG. 4.This supply is common to each pixel.

[0047] The VCOM electric potential is an alternating voltage that hassubstantially the same amplitude as the CS electric potential. Inpractice, however, since a voltage drop occurs in the TFT 51 resultingfrom a parasitic capacitance or the like while signals are written inthe pixel electrode of the liquid crystal cell 52 from the data line 54through the TFT 51, the VCOM electric potential must be an alternatingvoltage that is DC-shifted corresponding to the voltage drop, as shownin FIG. 4. This DC shift of the VCOM electric potential is carried outin the VCOM adjustment circuit 41.

[0048] The VCOM adjustment circuit 41 includes a capacitor C, a variableresistance VR, which is connected between an output terminal of thecapacitor C and an external power supply VCC, and a resistance R, whichis connected between the output terminal of the capacitor C and ground.The VCOM adjustment circuit 41 adjusts a DC level of the VCOM electricpotential supplied to the opposite electrode of the liquid crystal cell52; in other words, the VCOM adjustment circuit 41 applies a DC offsetto the VCOM electric potential.

[0049] In the liquid crystal display apparatus described above,peripheral circuits, such as the interface circuit 33, the timinggenerator 34, the reference voltage driver 35, the CS driver 38, and theVCOM driver 39, in addition to the horizontal driver 36 and the verticaldriver 37, are integrally disposed on the same panel (the glasssubstrate 31) as the display section 32 so that a display panelintegrating all driving circuits is achieved. Such a display panel doesnot require another substrate, an integrated circuit, or anothertransistor circuit, on the outside, thus miniaturizing the overallsystem and reducing costs.

[0050] In this driving-circuit-integrated liquid crystal displayapparatus, the timing generating circuit of the embodiment describedabove is used as the timing generator 34 generating various timingsignals for driving the display section 32. The timing generator 34comprised by the timing generating circuit generates various timingpulses, such as horizontal start pulses HST and horizontal clock pulsesHCK for driving the horizontal driver 36, vertical start pulses VST andvertical clock pulses VCK for driving the vertical driver 37, or pulsesnecessary for the CS driver 38 or the VCOM driver 39.

[0051] The timing generating circuit of the embodiment described aboveis used as the timing generator 34 so that the timing generating circuithas a wide operating margin even when transistors having wide variationsin their device properties and a large process rule are used for formingeach circuit on the glass substrate. Therefore, the liquid crystaldisplay apparatus, which TFTs are used for forming the peripheraldriving circuits integrally formed on the transparent insulatingsubstrate with the display section 32, has a wide operating margin.Additionally, the timing generating circuit enables a reduction in powerconsumption and a small layout area when the TFTs that have a largeprocess rule are used, thus contributing to the low power consumptionand the small size of the liquid crystal display apparatus.

[0052] This application is described with an illustration applied to aliquid crystal display apparatus that uses liquid crystal cells asdisplay elements, but the present invention is not limited to thisapplication. The present invention is applicable to display apparatuseshaving a level shift circuit disposed on the same substrate as a displaysection, such as electroluminescent (EL) display apparatuses using ELelements as the display elements.

[0053] The display apparatus typified by the liquid crystal displayapparatus of the application described above is suitable for a displayscreen component of compact and lightweight portable terminals such asmobile phones or personal digital assistants (PDAs).

[0054]FIG. 5 is an external view showing the schematic structure of theportable terminal of the present invention, for example, a PDA.

[0055] The PDA of the present invention may have a folding structure inwhich an openable lid component 62 is attached to a main body 61. Thetop face of the main body 61 has an operating section 63 consisting ofvarious keys of a keyboard or the like. The lid component 62 has adisplay screen component 64. The display screen component 64 is a liquidcrystal display apparatus that has the timing generating circuit of theembodiment described above, disposed on the same substrate as thedisplay section, as the timing generator.

[0056] The use of the timing generating circuit of the embodiment as thetiming generator of the liquid crystal display apparatus allows theliquid crystal display apparatus to have a structure in which drivingcircuits are integrated, a wide operating margin, low power consumption,and compact design. This liquid crystal display apparatus is used as thedisplay screen component 64, permitting a simplified structure,miniaturization, and cost reduction of the PDA. Additionally, this alsopermits low power consumption of the display screen component 64,resulting in increased duration for continuous use by battery-poweredoperation.

[0057] The application to the PDA is described by way of example, butthe present invention is not limited to this application. The liquidcrystal display apparatus of the present invention is particularlysuitable for general compact and lightweight portable terminals such asmobile phones.

[0058] As described above, according to the present invention, in thetiming generating circuit formed on the insulating substrate andgenerating the multiple timing signals having different frequenciesbased on the input master clock, the operating clock having a lowerfrequency than the master clock frequency is generated and then themultiple timing signals are generated based on this generated operatingclock having the lower frequency. This achieves a lower operating speed,leading to stable operation and reduced power consumption. Further, thecounter section is formed with a small number of steps so that a smalllayout area is achieved even when the circuits are formed includingtransistors having wide variations in their device properties and alarge process rule on the insulating substrate.

1. A timing generating circuit comprising: clock generating means formedon an insulating substrate for generating an operating clock based on aninput master clock, the operating clock having a lower frequency thanthe master clock frequency; and signal generating means for generatingmultiple timing signals having different frequencies based on theoperating clock generated by the clock generating means.
 2. The timinggenerating circuit according to claim 1 wherein the signal generatingmeans includes a counter section in which multiple shift registers arecascaded, the counter section performing count operations in synchronismwith the operating clock generated by the clock generating means; and asignal generating section that generates the multiple timing signalsaccording to combinations of shifted pulses output from the multipleshift registers.
 3. The timing generating circuit according to claim 2wherein the counter section performs the count operations in response tostart pulses generated in a predetermined period.
 4. A display apparatuscomprising: a display section having a matrix of pixels arranged on atransparent insulating substrate; and a timing generating circuitdisposed on the transparent insulating substrate together with thedisplay section, the timing generating circuit generating multipletiming signals having different frequencies required for driving thedisplay section in synchronism with a master clock externally input tothe substrate, wherein the timing generating circuit includes: clockgenerating means for generating an operating clock based on the masterclock, the operating clock having a lower frequency than the masterclock frequency; and signal generating means for generating the multipletiming signals based on the operating signal generated by the clockgenerating means.
 5. The display apparatus according to claim 4 whereinthe signal generating means includes a counter section in which multipleshift registers are cascaded, the counter section performing countoperations in synchronism with the operating clock generated by theclock generating means; and a signal generating section that generatesthe multiple timing signals according to combinations of shifted pulsesoutput from the multiple shift registers.
 6. The display apparatusaccording to claim 5 wherein the counter section performs the countoperations in response to start pulses generated in a predeterminedperiod.
 7. The display apparatus according to claim 4 wherein the timinggenerating circuit is formed on the transparent insulating substrateusing low-temperature poly-silicon or continuous grain silicon.
 8. Aportable terminal comprising a display apparatus as a display screencomponent, the display apparatus including: a display section having amatrix of pixels arranged on a transparent insulating substrate; and atiming generating circuit disposed on the transparent insulatingsubstrate together with the display section, the timing generatingcircuit generating multiple timing signals having different frequenciesrequired for driving the display section in synchronism with a masterclock externally input to the substrate, wherein the timing generatingcircuit includes: clock generating means for generating an operatingclock having a lower frequency than the master clock frequency based onthe master clock; and signal generating means for generating themultiple timing signals based on the operating signal generated by theclock generating means.